The present invention relates generally to method and apparatus for forming and insertable block tile, and more particularly to placement and routing of signals to and from a core embedded in a programmable logic device.
Programmable logic devices exist as a well-known type of integrated circuit that may be programmed by a user to perform specific logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and programmable interconnect structure are conventionally programmed by learning a stream of configuration data (bit stream) into internal configuration memory cells, conventionally block random access memory (RAM) to define how the CLBs, IOBs, and programmable interconnect structure are configured.
Accordingly, when embedding a core, sometimes referred to as an embedded core, into an existing FPGA design, a portion of the FPGA layout is exchanged for layout of the embedded core. This is sometimes referred to as creating a xe2x80x9cholexe2x80x9d in the xe2x80x9cfabricxe2x80x9d of the FPGA for insertion of an embedded core.
Once a portion of an FPGA is removed for an embedded core, signal lines, which may be thought of as conductive or metal lines, of the FPGA are abruptly terminated. Accordingly, for connecting an embedded core block to an FPGA, an area at the interface between the remaining part of the FPGA and the embedded core is reserved for interconnectivity. A layout engineer manually adjusts a layout working within this reserved operational interface area, i.e., namely creating FPGA-to-FPGA, FPGA-to-embedded core and embedded core-to-FPGA connections. This manual process is time consuming, especially in view of having to manually connect conductive lines in a limited space, which time intensive nature is exacerbated by having to search for metal levels.
Accordingly, it would be desirable and useful to provide method and apparatus for forming an insertable block tile for an embedded core into an existing integrated circuit layout that significantly reduces layout design time as compared to manual routing, as described above. More particularly, it would be desirable and useful if such method and apparatus could be integrated with place and route (PandR) tools.
An aspect of the present invention is a method for providing an insertable block tile for an integrated circuit having a region reserved for an embedded device. A physical layout database is provided for the integrated circuit. The region reserved is applied to the physical layout database. A portion of the physical layout database is removed in response to the region reserved. Terminated conductive line information is extracted from the physical layout database in response to the portion of the physical layout database removed. Layout names and associated coordinate information is identified for the terminated conductive line information extracted. The layout names are converted to schematic names. Logic names are mapped to the schematic names. The associated coordinate information is associated with the logic names to provide logic coordinate information.
An aspect of the present invention is an integrated circuit having an embedded core, where the embedded core is coupled to programmable logic to provide the integrated circuit. An input/output perimeter about the embedded core comprises a plurality of pins formed as extensions of conductive lines, whereby the pins are in integral alignment with the conductive lines for interconnecting the embedded core to the programmable logic.